Dtmb Error Correction Code Decoder-based Research And Design,

Since the birth of the 1st generation cellular communication system, the mobile communication technology has undertaken dramatic development, with evolutions of three generations in less than 30 years. Compared to other channels, the mobile channel is the most complex and unfavorable one. The resulting high bit error rate (5~10%) and low signal to noise ratio (SNR) put stringent constraints on the designing of the Encoder and decoders. Consequently, new error control coding techniques have been developed, such as BCH coding, TURBO coding, LDPC coding, etc. Especially, due to its low complexity and flexible coding structure, LDPC has become of a hot topic in coding research. Notable applications include DTMB, CMMB and DVB-S2.In DTMB, BCH and LDPC have been adopted as Forward Error Correction coding, with the former as outer coding and latter one as inner coding. We will study the designing of decoder and encoder for error control coding, including those for BCH and LDPC.To start with, we briefly explain the definition and concept of BCH and LDPC, followed by the introduction of error control solution in DTMB standard. After a thorough investigation of BCH decoding and encoding algorithm, we designed a novel decoding solution utilizing XOR-plane and AND-plane, to account for the single bit error feature of BCH in DTMB standard. A parallel BCH Decoder/encoder based on this algorithm is implemented on Xilinx xc2vp30 device. Simulation result shows that the processing speeds and resource consumption of our BCH de/encoder have meet the requirement of international standard.Then, we conducted investigation and simulation of common LDPC decoding algorithms, including LLR-BP, UMP-BP-Based algorithm, Normalized-BP-based algorithm and Offset-BP-based algorithm. Besides, we also proposed a modified minimum sum algorithm for DTMB standard.Finally, we discussed the hardware structure of LDPC decoder; analyzing the general structure of the decoder, stream line and quantization solution. According to the feature of QC-LDPC, we proposed serial-parallel combined structure and two levels of pipeline,then quantified by fixed-point simulation program to determine 8-bit quantization(1:4:3).Key components of LDPC decoder are designed and implemented on hardware as follows:VNPU,CNPU,Memorys.