IC Design Of MJPEG Encoder Based On FPGA

In recent years, the utility of consumer electronics continues to increase and image/video application is an essential feature. Data-compression is a key technology for image/video storage and transmission. JPEG is currently the most widely used image compression standard. It treats the luminance and chrominance respectively because the human eyes have different sensitivities of brightness and colourity. It also removes the high frequency section in the picture which is not as sensitive as low frequency section. Therefore JPEG image compression standard can guarantee the quality of the picture, but also has a high compression ratio. The algorithm has three techniques for image compression which are composed of DCT transform, quantization and Huffman coding.The first two techniques are lossy, and the last is lossless. MJPEG video compression format is based on JPEG standard. MJPEG has only JPEG compression in the frame and no inter-frame compression, which is different from general video compression standard. Loss of data in a frame will not influence the other frames. So it is particularly suitable for transmission in weak channel, like mobile applications.This paper implements the real-time MJPEG compression and transmission based on FPGA which is verified successfully. This paper first gives a brief introduction of the basic principles of FPGA, the development process and common used tools. The design philosophy and code rules are also discussed in this part.Then it presents a specific algorithm of JPEG encoding and its implementation on FPGA. In this section, the whole design is given a reasonable division considering the characteristics of FPGA, and each sub-design (module) is given a detail description and a specific implementation.Finally, it is the design verification. Validation includes FPGA hardware design, verification-required modules design and a detailed verification flow. To achieve the communication between FPGA and PC, some modules are required, like UART module and network transimission module. There are two verification flows:static data validation and dynamic data validation. The former downloads the data that will be encoded to the FPGA to verify the design, and the latter implements real-time video stream encoding.For the future reuse of the module which is designed in the paper, good coding rules and interface specification are strictly observed. Each module's external interface is simple and practical, so that it can be used for the other systems. The proposed implementation of relevant algorithm can be applied in a variety of video encoders and decoders.