| Timing, area and power are important factors in chip design. Along with advances in semiconductor technology, the attention of power factor in chip design gradually increased. Industry has a set of low-power design methods. Recently, we designed a chip with low power implementation and verification. We used part of IEEE1801 standard based Unified Power Format (UPF) technology, successfully completed the whole flow of RTL to GDSII. The chip has been manufactured and tested, the low-power design methods of this chip has been verified.This paper first introduces the low power technology of physical design. We describe the theory of power in CMOS circuits, includes dynamic power and static power, and the relation of dynamic power and static power. Clock gating, multiple threshold voltage logic, multi-VDD and power gating technology was introduced. The strategy and difficult of multi-VDD was analyzed. Power gating is a complicated low power design technology. There are some special PM cells, such as MTCMOS, isolation cell, retention registers. The power switch network and power gating controller should be carefully researched.Synopsys UPF low power design flow was introduced, and the UPF file was analyzed carefully. The low power design intent was described by UPF, such as whole chip power manage supply network, the insertion of isolation cells and level shifters, power switch cells. The power grid and strap, the relation of power rails and RTL description was included by UPF file. The UPF files contain:describing power domain, describing power network, describing power switch cells, describing isolation cells, describing level shifters, describing power state table.Finally, the physical design of SEP6010B was implemented by Synopsys EDA tools. The flow contain:floor-plan, creating voltage area and MTCMOS, placement and control wire connection, PNS, CTS, routing. |
