Researches On Power Optimization For Network-on-Chip Using Power-Gating

As the development of microprocessor,the number of computing cores grows rapidly,hence,an energy-efficient and scalable communication is more and more important for cores.Network-on-Chip,which is widespread applicated in modern high performance microprocessors,is a flexible and scalable scheme for multi-core communication with respect to traditional bus architecture.With the growth of the processor performance,the number of cores increases,the scale and complexity of Network-on-chip is increasing,which leads the power of Network-on-Chip grows.Power has been one of key factors which restrict the development of networks.How to do power optimize,is an international hot research topic.Run time power-gating,which park network components to save network power,is a hot research on Network-on-Chip power optimization.Ensure the network connectivity,avoid frequently on/off network components,and rapidly adjust to workloads' variation are all difficulties in power-gating.This paper researches on power optimization based on power-gating,the main works and novels as follows,1.We propose a novel network-on-chip router design with heterogeneous virtual channels on power optimization.There are multiple virtual channels,which contain a set number of buffers each,in traditional network routers.Adding a buffer gives us a place to store the packet while for the second channel,allowing the allocation of the second channel to be delayed without complications.Adding buffers to networks results in significantly more efficient flow control.A significant part of the No C's power is consumed in the router buffer.Bufferless router(router without buffer or virtual channel),which consumes low static power,is proposed in international research area recently.However,with the workloads increasing,bufferless can not afford the traffic for its misrouting or packet dropping.In this paper,we propose HVCRouter,a novel No C router design with heterogeneous virtual channels.In particular,HVCRouter incorporates a bufferless channel to respect its power efficiency at low network load.HVCRouter employs a fine-grained power gating algorithm which exploits power saving opportunities at both channel and buffer levels simultaneously,and is able to achieve high power efficiency without degrading performance at varying network utilization.2.We propose a hybrid Multi-No C design adopts a hybrid CMesh and Mesh(s)architecture on power optimization.In contrast to the conventional No C designs,call them Single-No C,a Multi-No C(multiple network-on-chip)design,partitions wires and buffers in a conventional No C into several subnets,and connects each node to corresponding routers in all the subnets.The layered architecture makes Multi-NoC more suitable for power gating,due to the opportunities of turning off some subnets while not damaging network connectivity.Catnap makes the first attempt to apply power-gating on Multi-No C architecture.Catnap adopts a homogeneous multi-subnet architecture.However,at low network utilization,which often happens for many real-world applications,mesh network consumes considerable leakage power,therefore we are motivated to optimize Catnap at low network utilization.In this paper,we propose a hybrid Multi-No C design,called HM-Mesh.HM-Mesh adopts a hybrid CMesh and Mesh(s)architecture,and leverages CMesh network to respect its power efficiency at low network utilization.HM-Mesh is able to adaptively schedule packets to different subnets according to the network load,and smartly perform power gating to achieve good energy efficiency.3.We propose a novel low power Multi-No C design with distinct routing algorithms for different subnets.Currently,processor designers strive to send under-utilized cores into sleep states in order to reduce idling power and improve overall energy efficiency.However,even in state-of-the-art CMP designs,when a core goes to sleep the router attached to it remains active in order to continue packet forwarding.We enable power gating for the lowest-order subnet by using a recently proposed CBCG routing algorithm for it,CBCG is a deadlock-free methodology for irregular network topology,where some of the links/routers are out-of-service.At low network load,CRA will power off higher-order subnets and some of the routers in lowest-order subnet to minimize leakage power,while retaining network connectivity and not impacting performance.Since the adaptive nature of the CBCG algorithm,its cost is higher than the classical dimension-order algorithm,when the traffic is high,it will incur performance degradation.In that case,a congestionaware power gating policy enables CRA react quickly to turn on more components/subnets to mitigate congestion.Together with a smart packet scheduling algorithm,CRA could save more energy.4.We propose a novel heterogeneous Multi-No C design.Recent studies have explored several power-gating optimizations for No C at different levels of granularity,i.e.,buffer-level,router-level and subnet-level.In this paper,we propose Chameleon,a novel hetgeneous Multi-No C design.Chameleon leverages the buffer-level power optimization technique by integrating one subnet without buffers to constitute a heterogeneous architecture.Chameleon performs power gating at both router and subnet granularity to capture more power optimization opportunities.In addition,Chameleon employs a congestion-aware traffic allocation policy which ensures no wake-up delays will be encountered,and efficiently avoids overloading any subnet.Chameleon is able to achieve both high power efficiency and good performance at varying network utilization.