Research And Implementation Of Fault Simulation System Based On CPCI Bus

With advantages of high reliability, PnP (plug and play) and hot swappable, CPCI bus provides good support for design of high-avaibility computer system. Currently, FT (fault-tolerant) computer system based on CPCI has been widely used in telecommunications, network, transport and industrial control and other fields. Therefore, the need of FT mechanism verification tools based on CPCI bus is particularly urgent.This paper first studied the topology, electrical specifications of PCI and CPCI. The limitations of the traditional hardware-embedded fault injection method of PCI bus were analysed and a scheme based on PCI-to-PCI Bridge IP cores and FPGA technology was proposed. This method solved the synchronization and delay problems of CPCI fault injection.The hardware, software and FPGA logic of fault simulation system were designed and implemented in detail. 32-bit faults can be injected into the PCI address/data bus simultaneously. Location, orientation and type of faults, which including stuck-0, stuck-1 and bit-flip, can be specified in software. Faults can be injected permanently, transiently or intermittently. An improved probability triggering method with precision of 0.01% which improved the accuracy and controllability of fault injection was achieved based on random triggering.At last, fault-injection experiments were carried out on a typical CPCI system. Experimental results show that the method is feasible. It is with good performance and accuracy, and its functions meet the design requirements. The method not only can be seamless transplanted to the PCI platform, expands the scope of use, but also can be further improved to achieve more fault types and other features.