Functional Verification Of UART Module Based On SystemVerilog

With the development of semiconductor techniques, the scale of chip design becomes larger and complexity increasing. The traditional verification methods have failed to meet today's needs in coping with many problems. The new efficient verification methods, based on the scientific verification methodology, can guarantee the successful completion of chip's functional verification.The contents of this paper are from a joint project with a word famous electric company of Dalian. It involves carrying out a comprehensive front-end functional verification of RTL-level for a UART interface module whose parameters are configurable, including VMM verification and formal verification, to ensure that the module's design meets the proposed functional requirements.This paper introduces the VMM verification methods and formal verification methods that are based on SystemVerilog language, as well as the usage of VCS and 0-In verification tools. This paper also carries out a functional verification for the UART interface module using the two methods above-mentioned. Following the UART module's design requirements, the writer decomposes the test points and assertions which need verifying, and builds a multilevel, reusable and extensible VMM verification platform and a formal verification environment. The writer also designs and writes test cases and assertion checkers, as well as detects one code error and 12 lines'redundancy code. Based on the modified code, the VMM verification's functional coverage and code coverage have reached 100% and 94.47% respectively, without any logical error. At the same time, all the formal verification's assertion checkers have passed, which meets the export conditions of the UART model's functional verification.This paper proposes a functional verification method combining VMM verification and formal verification using 0-In instrument. First, we should do a formal verification to test the timing-related attributes, and detect the code bugs; then we can carry out a VMM verification, to test the correctness of logical functions. This method overcomes the traditional verification method's shortcomings of the low reusability of verification platform, the low coverage of targeted incentives and the lack of completeness because of over-reliance on simulation, which can improve the efficiency and quality of functional verification.