Structure A Reference Module Of ISO14443Communication Interface In VMM Verification Platform

With the increasing scale of digital integrated circuits, the design is more complicated, the difficulty of verification also increases. Adding a new feature needs more than one test case. In a real project, verification has taken up70%of the entire development cycle. How to build an efficient verification platform and develop a excellent verification environment has been priority in current integrated circuit design work.The application of dual interface card is increasing rapidly among world nowadays, which suggests a promising future of dual interface card application. In this article, for dual interface cards that meets ISO14443protocol, we would provide a more efficient verification method for non-contact RF communication interface module, which is adding reference module built by high abstract language SystemVerilog based on traditional VMM random constraint incentive-based verification platform. Golden response provide by this reference model makes DUT functional check more simple and efficient. Also, it improves portability and reusability of verification platform and shortens the chip development cycle.This paper first described the VMM verification methodology, and after to introduce the ISO/IEC14443communication protocol and the DUT RTL design specifications, followed by the traditional verification platform to make a comparison with the reference model verification platform description. In this thesis, the focus of the work is designed to prepare the RF communication interface reference model, the paper focuses on the description of the design method of the reference model and the code structure, the reference model is designed to prepare complete embedded traditional verification environment, front-end RTL simulation, simulation results show that the traditional verification environment reference model can improve verification coverage.