Neural Network Algorithm To Implement Based On FPGA

Simple Adaptive Control Algorithm has some characteristics of simple control structure,control algorithm is almost nothing to do with the controlled plant and so on. SAC can track the performance of ideal reference model. Combined Simple Adaptive Control and Neural Network, at the same time, optimized weights of Neural Network by Genetic Algorithm, the new control method integrated simple structure,less regulated parameters of SAC, approximations to the nonlinear function,a wide range of mapping ability of Neural Network, global convergence of Genetic Algorithm. The new control method meets high-precision, high-quality of industrial control, has the extensive development foreground.FPGA, as a semi-custom circuit of ASIC field, not only solved the shortcomings of custom circuits, but also overcame the disadvantages of original programmable devices with limited gate circuits. With the expanding scale of FPGA, FPGA can meet the speed and flexibility requirements of system. So FPGA can be used as an ideal device for algorithm implementation. Algorithm was described by hardware description language (for example VHDL, Verilog) and then downloaded to FPGA device using logic synthesis tools, the hardware implementation method is faster than other methods. Internal logic of FPGA can be changed according to requirement, so FPGA has higher flexibility than other hardware design methods.The paper studied on algorithm implementation based on FPGA, the algorithm is that Neural Network Simple Adaptive Control based on Genetic Algorithm (GA-NNSAC).First, GA-NNSAC control algorithm was simulated in MATLAB platform. Simulation results showed that Genetic Algorithm can optimize weights of Neural Network quickly. Finally, the optimal weight was obtained. The effectivity of the control algorithm is proved by means of simulation to nonlinear controlled plant.Second, system was designed by top-down,stepwise refinement method. System was broken down into various sub-modules gradually until sub-modules were in a reasonable relationship and easy to implementation. Each module was encoded with VHDL and generated schematic symbols after compilation.Finally, the waveforms of the major modules were simulated using QuartusII9.0 simulation tool of Altera Company. After sub-modules were proved to be correct, the top-level module was simulated and tested. The result of simulation showed the design was correct and reasonable.