Research And Design Of High-performance DSP Communications Interface

DSP (Digital Singnal Processor), a diversified high-performance microprocessor, is widely used in data communications, mass storage, voice processing, automotive electronics, consumer audio and video products and other fields. In recent years, digital consumer electronics has been in great demand in the Chinese market. A great variety of the products, the complete functions of the products as well as the increasing penetration of the products have broadened and deepened the application of them. This not only requires constantly increasing high-speed computing of DSP digital signal but also requires them become more compatible, more flexible and more convenient.This paper focusing on 32-bit high-performance DSP peripheral communication interface, carries out a detailed study and design on high-speed synchronous serial interface circuit SSC (Synchronous Serial Controller) with top-down design approach. By setting multiple parameter settings, SSC interface can be configured, flexible, and compatible. High-speed synchronous serial interface supports full-duplex and half-duplex synchronous communication with communication speed rate, communication data width, clock polarity, clock phase and data shift direction configured to enable it communicate with Serial Peripheral Interface (SPI) compatible devices or other synchronous serial devices. Processors and peripherals mainly applied into the DSP communication between the use of master / slave mode can also be used in communication between multiple processors.This paper first analyzes through the protocol among I2C, UART and SPI, three serial communications, and summarizes the advantages and disadvantages of it. According to the design goal of SSC interface, this paper tries to make appropriate improvements improvement on SPI protocol and makes SSC interface communication protocol. In this way, this paper defines the SSC peripheral interface module interface signals, divides sub-modules according to function of the design, determines the connecting signals between sub-modules, provides a complete and signal connection diagram, conducts researches on each sub-module with certain preoccupations and describes each sub-module circuit with VHDL language. Finally, using ModelSim by simulation and verification and through integration with DC, this paper analyzes the area and power of SSC interface. The results show that when using TSMC 65nm process technology library, the bus clock is 150MHz; the maximum data of transmission rate is up to 75Mbit / s; the area is 11868 um2; the power consumption is 424uW. It is well positioned to meet the design requirements.