FPGA Design Of The Digital Contest Manager Of Digital Television System

Digital TV head-end system, as the core devices of digital television industry, is the processing center of television programs and other applications. Traditional digital TV head-end system use ASI (Asynchronies Serial Interface) to transmit data from satellite, local programs, SDH data and broadcasting data services. All multi-ASI data would be sent to the matrix distributer and then to the re-multiplexer to decode and scramble. Other transmition devices would add special information such as signatures and advertisements before sending them to next sub-systems.Along with the rapid development of digital TV industry, mostly the more and more programs from network sources and customized data services, the traditional head-end system has many difficult in extensibility and adaptability. Compare to the older structure, the new generation of digital TV system based Ethernet better fit the trend of today.The Digital Contest Manager (DCM) is the core processer of new generation of digital TV system which can function as matrix distributer, re-multiplexer and scrambler. The DCM receives both ASI and Ethernet data as center node of the whole system. It uses universal Ethernet switchboard to transmit data from local and far end sources. Television programs, data services and other applications received from gigabit Ethernet ports can be handled and transmitted directly. This equipment can drastically simplify the head-end system which could improve the whole cost and stability in addition.After sufficient investigation about the market requiment of FPGA system in the Digital Contest Manager, this paper choosed the Altera/Cyclone III EP3C120and Quartus II design environment and accomplished the system design, module design, software implement, function simulation and verification on board. To insure the fuction and stability, the optimization of software code and module design is also finished after amount of system level function and stability tests.The FPGA system of the Digital Contest Manager can basically meet the requirements of the system design after these verifications above. In the design process, gave a full account of the system's function, expandability, modular design, and stability. This paper would provid good technical reserves for the further development of the Digital Contest Manager.