The Design And Implementation Of Ddr3 Memory Interface Circuit

DDR memory is a kind of high performance and low cost memory solution, as a main external memory of the central processing unit (CPU). DDR memory is widely used in PC, servers and the SOC designs. It is used to store data and programs, and called "DDR SDRAM". As the performance of CPU greatly increased, the performance of DDR SDRAM improved as a result.At present, the mainstreams for industry are moving from DDR2 to DDR3, which has not only lower power consumption, but also higher speed and capacity. While in use of DDR3 SDRAM, the main challenge for user is that the requirement for high speed I/O. That is because when the operation speed reaches up to 1Gbps for interface, the I/O performance became very critical, even the bottleneck of the system performance. So the development of a high speed DDR3 I/O is a requirement from DDR3 application perspective. When in development of DDR3 I/O, designer would realize that the digital signal on interface is not as it’s expected to be, and the signal integrity problem will be one of the main concerns for designers.DDR3 I/O is a mix signal high speed I/O; the main challenges for IP designer are explained as below. First, high speed MOS transistor from deep submicron process should be chosen for the design. Second, circuit structure should be chosen carefully for high performance operation. Third, the signal integrity problems should be taken into consideration at the beginning, and simulations done based on proper models. At last, layout area should be constraint and robust ESD performance is a concern.In this paper, a DDR3 I/O is developed that’s base on SMIC 65nm LL process. The operation speed could up to 800Mbps-1600Mbps under 1.5V voltage. The I/O compliant with JEDEC DDR3 specifications, and could be used in DDR3 PHY as an IP for DDR3 controllers.