Research And Implementation Of Mid-Frequency Digital Downconversion Receiver Based On FPGA

As the development of software radio theory and digital signal processing technology, varies kind of digital signal processors are apply in our life, and the FPGA is one of them. As the market itself, it is very normal to see the DSP platform based on FPGA. FPGA is programmable, digitization. So it is very easy to update. And during the processing of the signal, the mid-frequency digital downconversion part is one of the most important parts in the receiver. So the receiver base on mid-frequency digital downconversion appears in the DSP field.This thesis firstly analyzes the development and the present research status at home and abroad, and then states the band-pass sampling theorem and the relevant baseband signal demodulation based on software radio theory; then analyzes the general signal synchronization algorithms in digital receiver. This thesis summarizes several signal synchronization technologies, and then from FPGA application and this article, presents a method of mid-frequency digital downconversion receiver based on FPGA. Then proved the method is feasible from the system simulation in matlab. This method utilizes the carrier recovery algorithm based on costas loop in the downconversion and demodulation of the QPSK signal. With the help of PLL reconfiguration, we enhance the flexibility of the system, then we use the signal synchronization algorithm base on Gardner algorithm and Barker Code. In the end, we complete the algorithms and the modules of the system using Verilog language and Altera QuartusII Software.