Pipeline Adc Offline Digital Calibration Circuit In The Design And Implementation

Analog-to-Digital Converter (ADC)’s performance plays a significant role in the entire electronic system. Among the various types of ADCs, pipelined ADC, with its both high speed and high resolution, is occupying a very important postion in some applications such as wireless communication. As the trend of digital circuits taking place of analog circuits becomes more and more obvious, ADCs’digital calibration is drawing more and more attention in the recent20years.This paper first introduces pipelined ADC’s basic architecture and major error sources. Then,1.5-bits stage of pipelined ADC, which is based on redundant coding and has remarkable advantage in architecture, is represented and taken as an example to analyze the impact on pipelined ADC stage’s performance of several error sources.To meet the need of project,"ADC with high accuracy+Offline digital calibration" is chosen as the project’s scheme. Offline algorithm is simulated on the MATLAB platform which is structured on the basis of "4+4+4+3" four-stages pipelined ADC’s architecture. The simulation result demonstrates a significant improvement of ADC’s performance after calibration.Based on the mathematical model created by MATLAB, Verilog HDL is employed to design the Offline digital calibration circuit’s RTL model. Subsequently, the RTL model and its sub-modules are simulated in ModelSim. The simulation result indicates that RTL model has basically achieved the goal of algorithm’s design.Based on the RTL model, the standard work flow of Synopsys Corporation is utilized to complete Offline digital circuit’s ASIC implementation. The whole ASIC implementation flow consists of logic synthesis(by Design Compiler), static timing analysis(by PrimeTime), formal verification(by Formality), layout design(by Astro) and post-layout simulation(by ModelSim). The post-layout simulation result, which is consistent with RTL simulation result, illustrates ASIC implementation’s success.