Ldpc Code Research And Decoder Of The Fpga Design

Low-density parity-check codes (LDPC codes) is another important area of thechannel encoding and decoding after Turbo codes. Since it was proposed in1960s andwas rediscovered in1990s, it has become a hot spot and has been researchers’sensation due to its excellent decoding performance and lower complexity. Currently,LDPC codes have been applied in DVB-S2systems as coding standards. At the sametime, it has become a focus encoding scheme in the4G communications and itsapplication prospect grew quite broadly.Based on the two classical decoding algorithms, this paper proposed an improvednew algorithm based on loop detection, and designed a NMS algorithm decoder bycombining with the FPGA. The detailed work was as follows:At first, this paper analyzed the principles of LDPC codes, and discussed twoconstruction methods of LDPC codes based on its encoding complexity. Bycomparing with the structure of check matrix H, the thesis simulated the performanceof regular and irregular LDPC codes, the four circles in check matrix impacting ondecoding performance.Then, as for error correction decoding performance and computationalcomplexity, this paper focused on two types of decoding algorithm: hard decisionalgorithms (including BF algorithms, WBF algorithm, MWBF algorithm, RRWBFalgorithm) and soft decision decoding algorithm based on BP algorithm (Log-domainBP algorithm, MS algorithm and the NMS and OMS algorithm).Next we proposed anew hard decision algorithm (namely NBF/LD) on basis of "loop detection"mechanism. By comparing with other hard decision algorithm, Simulations showedthat this algorithm’s decoding performance improved quite obviously with lowercomputational complexity.Finally, considering the compromise between the logic resources and the clockfrequency, the design of decoder based on FPGA was adopted partial-parallel method.The paper analyzed the various parameters effecting on the NMS algorithm, gave thestructure module of the decoder. Every module used the Verilog language under theQuartus II development platform, the functional and timing simulation of each module was confirmed to meet the requirements of the design.