Study And Design Of Automatic Modulus Controlling High Quality All Digital Phase Locked Loop

With PLL has played a unique benefit in various applications and the continuous development of integrated circuits, the design of phase-locked loop and the application of feedback control technology take the focus of attention today. Based on analysis of a large number of domestic and foreign technical literature on the basis of summing up the development status and the technical level of phase-locked loop, elaborated the module structure and the basic principles of the DPLL circuit, analysis the structure and the characteristics of the DPLL main module, designed a high-precision automatic mode control of variable speed all-digital PLL system.The system uses the output signal phase of fast capture area, slow fishing area and locked area behind the switch, and adjust to achieve real-time control loop bandwidth automatically, which improves the speed lock greatly, overcome the contradictions of the loop capture smell and noise immunity. With the synchronization set-up time is short, anti-interference ability, high control precision, static difference is small, simple structure and easy integration of characteristics can be made on-chip phase-locked loop.Phase detector constituted by the edge of the trigger, using the difference of the delay time among internal logic gate of the trigger; make it receive the input signal only when the up edge clock occur.The function of the Digital loop filter (DLF) is to eliminate the high frequency components of the phase output of the phase difference signal PE, guarantee the stable performance of the loop, actually, it can achieve by a reversible counter variable model (with modulus K).K reversible variable-mode counter signal according to a difference of PE to be addition and subtraction.Digital divider, N divider is a simple addition to the counter N.N divider output pulse subtraction circuit further N pulse frequency, making the loop output signal fout.This design focuses on the design of K change of feeling on the counter, K reversible variable-mode counter modulus K on the DPLL’s have a great impact on performance. Counter modulus K of the value of the input signal can be phase jitter, increasing the modulus K, to improve the noise immunity of DPLL, but will lead to greater capture time and narrow capture bandwidth.Add an automatic change-mode controller to the original all-digital phase-locked loop on the basic principle, control on the digital loop filter modulus, to reduce the capture time, a view to increasing the operating frequency. This design uses VHDL language to program the entire PLL system, functional simulation in Model Sim, and achieved the anticipated requirements successfully.PLL is widely used in the discussion of the basis of several common applications; this paper focuses on the design of the new all-digital phase-locked loop in the time-digital converter.