Research And Design Of A CMOS Millimeter-Wave Low-Phase-Noise Cascaded PLL Frequency Synthesizer

In wireless communication systems,frequency synthesizers as the core module of RF transceivers,mainly provide high-performance local oscillator signals for transceivers.In recent years,with the increasing demand for high-speed communication,the millimeter-wave band have become increasingly popular due to its wide communication bandwidth.In the millimeter wave frequency band,the continuous improvement of system requirements in low phase noise and the deterioration of frequency synthesizer noise performance become an inevitable contradiction,and this is particularly evident in radio frequency receivers.In traditional single-stage millimeter wave phaselocked loops,the system may have poor phase noise due to a large frequency division ratio.However,cascaded dual phase-locked loops are gradually attracting attention due to their unique structural advantages and the ability to achieve lower phase noise performance.Finally,a CMOS millimeter wave low phase noise cascaded phase-locked loop frequency synthesizer is designed in this thesis by focusing on the research in low phase noise millimeter wave frequency synthesizer.First of all,the existing problem of a single-stage millimeter wave phase-locked loop frequency synthesize is discussed in this thesis,and then the advantages of cascaded phase-locked loop compared to a single stage structure are summarized by analyzing the two structures of the system.Finally,a millimeter wave frequency synthesizer based on an all-digital phase-locked loop and a sub sample phase-locked loop is designed.In order to alleviate the impact of bandwidth on the in-band and out-of-band phase noise of the single-stage millimeter wave frequency synthesizer and suppress the in-band and out-of-band phase noise,the loop bandwidth for achieving the optimal total output phase noise of the two-stage phase-locked loop in the frequency synthesizer is derived by combining the important parameters of the two-stage phase-locked loop.An all-digital phase-locked loop consists of a frequency and phase detector,a time to digital converter,a lock detector,a digital loop filter,a digital-controlled oscillator,and a frequency divider.In order to solve the problem of selecting the wrong frequency band in the loop due to initial phase error when traditional automatic frequency calibration modules are used to achieve frequency band selection,a lock detector that sequentially detects the lock state of the coarse,medium,and fine tuning processes and generates a control signal to switches the circuit to the next tuning process is proposed in this thesis.The automatic loop gain control technique is used to adjust the loop bandwidth in the digital loop filter,which can not only shorten the lock in time of the loop,but also reduce the in-band phase noise of the phase-locked loop.The noise circulating technique is adapted in oscillator to reduce the injected noise of resonator,thereby improving the phase noise.The sub-sample phase-locked loop consists of a frequency locked loop that implements the frequency acquisition function and a sub-sample loop that implements the phase locked function.The reference clock of the frequency locked loop is provided by the output signal of the all-digital phase locked loop after frequency division,which not only achieves frequency locking in the millimeter wave frequency band,but also avoids locking the output millimeter wave frequency of the sub-sample phase-locked loop at the higher harmonics of the output frequency of the previous stage of all-digital phase-locked loop.The output signal of the first stage all-digital phase-locked loop is used as the reference signal to achieve phase locking in the sub sample loop.At the same time,the loop removes the frequency divider,which can achieve lower phase noise.Finally,a cascaded phase-locked loop millimeter wave frequency synthesizer is designed in the65 nm CMOS technology.The overall circuit layout area is 1060μm×854μm.The post simulation results show that under 1.2V power supply voltage,the power consumption of the frequency synthesizer is 46.8m W,the output frequency range is 22～26GHz,and the locking time of the loop is less than 25μs.When the output frequency is 24 GHz,the phase noise at the 1 MHz frequency offset is-104.8 d Bc/Hz.