Based On FPGA And DDR2Video Buffer Of Design And Implementation

As the development of information technology, the application of the embeddedsystem has become more and more often in various fields. On one hand, mass cachememory has been applied widely in the video system but the price of High speed andlarge capacity cache chip is quite expensive. On the other hand, the traditional storagemedia can not satisfy the demand of the bigger bandwidth, especially when it requiresthe function of massive data MIMO.In recent years digital TV technology has developed significantly which meansnumerous data need to be spread at the same time. To achieve this high-speed massivecache, which meets the requirements of both speed and capacity, need to be foundduring the operation of video system. The combination of FPGA and DDR2SDRAMhas been considered as one of the best solutions of the acquisition system of thehigh-speed video data, because of its suitability and flexibility as well as theadvantages of high speed, huge capacity and the reasonable price. This article isaimed to provide a new research idea of the design of the massive storage by focusingon the improved MIMO technology of the massive data storage based on thecombination of the FPGA and DDR2SDRAM. In the first part of this article itintroduces the timing characteristics of DDR2SDRAM at work and the function andrequirements of the DDR2SDRAM controller. Then the most popular designframeworks are listed one by one. In the following part a high-speed storage solutionfor the video cache is put forward by the through analysis of the storage principle ofthe FPGA and DDR2presented by Xilinx company. This solution is able to meetrequirement that there must be8MB for each storage channel. This research successes to accomplish the design of the high-speed and massivestorage solution of multi-channel data based on the combination of the FPGA andDDR2SDRAM, and this solution can be applied in the modulator system on thebasement of DVB-C which satisfies the requirement of the high-speed, massive andmulti-channel storage. Besides, the design of DDR2memory interface with Spartan3FPGA by Xilinx is also introduced in the later part of this research in order to displaythe reliability and convenience of this interface design with the help of the I/O moduleand logical resource provide by the FPGA. To insure the reliability of the storageinterface system, a series of simulations and analysis of time sequence has been done,test results showed that the design meets the system requirements, while the I/Omodule and other logic is also configured and Instantiated by the RTL code. Theconcrete findings are as follows:(1) In the FPGA design, using a wireless communication system of multipathtransmission theory to the framework system design.(2) This video buffer are achieved for a transmission character with FIFO feature,and make a convenient interface to the complexity of the timing of high-capacity,multi-channel, high-speed storage medium applications.(3) This video buffer to meet the IPQAM devices for data storage requirements,achieve the successful removal of a video signal for the purpose of network jitter.