Research And Detailed Design On Inter-frame Prediction Module In Real-time H.264HD CODEC

With the rapid development of digital media technology, videoencoding/decoding is getting more and more important in multimedia systems.How to obtain a good image quality and low-bandwidth signal transfer in alow level of storage condition has become two main problems in videocompression. ISO/IEC and ITU-T, the two international standardizationorganizations has developed next-generation video compression standardH.264together.H.264video coding standard commit itself to improving the codingcompression efficiency and adaptability to different networking environments.H.264standard carries forward the merits of the previous standards and it alsotakes in a large number of new technologies, including three or more itemsassociated with the motion estimation. There are quarter-pixel precisionmotion estimation, seven kinds of variable block size partition matching andmulti-reference-frame technique. On the other hand, in order to improve thecoding efficiency, H.264uses a lot of algorithms with high complexity, and itincreases the difficulty to realize a real-time encoding/decoding system.Based on the analysis of each functional module in H.264codec, we can seethat the inter-frame prediction (motion estimation) module may take up over70%calculated amount in the whole codec system. Therefore, theimplementation of inter-frame prediction module is the key to achievehigh-definition real-time video codec system. So, from the point, this articlestarted with a detailed study of every aspect of the H.264standard processesand several hardware reference implementations, put forward evaluations andimprovements, then proposed my own inter-frame prediction architecture inH.264codec, as follows: Hardware inter-frame prediction algorithm can mainly be divided intofour categories: prediction motion vector adjustment strategy, search rangecenter adjustment strategies, algorithm to reduce the computationalcomplexity and to improve the search range, and the hardware cost-savingcompromise. These algorithms can either be used alone, or be chosen together,depending on the need of coding efficiency and hardware cost. After thedetailed analysis of the H.264standard codec process, this article referred tosome reference implementations, and brought up a variety of new hardwarealgorithms of inter-frame prediction. It also used H.264standard softwaresource code JM to get the realization, comparison and simulation of differentalgorithm, pointed out their pros and cons, and made some improvements inthe search mode, downsampling mode, search range and search order to anumber of outstanding architectures. At last, we chose out of the Level C+data reuse algorithm as the inter-frame prediction module framework in ourreal-time HD H.264codec.Then this paper took module as a unit, analyzed all the difficulties inhardware implementation one by one, designed the meticulous architecture,including the design framework, data organization strategy, various supportedmode, estimation in bandwidth and performance, and even some designdetails of this motion estimation module in real-time HD H.264codec. Froma careful assessment, we can see that this proposed structure can significantlyincrease the on-chip memory data reuse, reduce bandwidth and gate countrequirements, cut down the computational complexity, achieve real-timecoding with a lower working clock frequency, and it is easy to realize inhardware. Compared with reference hardware implementations, our proposeddesign is better in the comprehensive evaluation in performance, bandwidth,gate count, memory, and overall image quality.