Design And Implementation Of Multi-Channel Solid State Disk

Because of the advantages, such as high performance, low power consumption andlow noise, SSD (Solid State Disk) is the ideal succedaneum of traditional magnetic diskdrives. Because of the latency, the NAND flash memories offer poor performance andread/write bandwidth is limited. As the emergence of MLC (Multi-Level Cell) Flash, thisproblem becomes more serious.The bandwidth of single-channel and single-chip NANDflash-based storage devices is far from satisfying the requirements of users.In order to solve the bandwidth bottleneck of flash memories, SSD employsmulti-channel architecture in which it is possible to access the NAND flash memories inparallel for amortizing the long latency of flash memories and increasing the bandwidth.We analyze the multi-channel architecture of SSD, propose the correspondingmanagement architecture. The proposed design and implementation includes division ofsystem area and data area, queue management, buffer management, parallelismmanagement and flash translation layer.We presents a multi-channel SSD, which effectively raising the system capacity andincreasing the bandwidth by maximally exploit the channel parallelism and flash chipinterleaving. In order to support popular interface, we design the command queue,submitting-queue and completed-queue. And the high-performance data buffer designedfor this structure improves the overall performance and life of flash memory, whichaccessing hot data in SDRAM and remove unnecessary duplicate writes to flash by updatein SDRAM. In addition, we design a FTL (flash translation layer) for SSD, includingaddress mapping, garbage collection, etc. As the SDRAM overhead of page-mappingscheme, We propose a Workload-Aware Flash Translation Layer(WAFTL), whichSelectively caches page-level address mappings and two-mapping approach, whicheffectively reduces the size of mapping table in SDRAM.The flash controller is based on Altera’s EP2C35F484C6N FPGA, which is low-endFPGA.Therefore, the FTL performance FTL is40%of Flash controller. Read and writeperformance improved compared with single-chip flash.