| With the continuous scaling of Very Large Scale Integrated Circuit (VLSI), BE-OL(Back end of line) is more and more important in the whole manufacture process.Cu/low κ interconnect has been introduced to reduce the RC delay, which affectsthe performance of circuit in100nm copper interconnect or beyond. With the de-velopment of technology and material, it is recognized that the previous capacitancemodels are not suitable for today’s BEOL interconnect. In the same time, alloy seedtechnology has been applied to decrease the effect caused by the scaling of barrier andincrease the reliability of circuit.In this study, we discuss capacitance model building for28nm Cu interconnectand the effect of thermal treatment on Cu interconnect wire from the process perspec-tive. We extends the previous65nm field-based model to integrate the impacts of thetechnology innovations like transition layer, barrier and plasma damage layer. Themodel derivation is based on careful analysis of the electrical fields between lines andplates and the total capacitance is decomposed into different building components, i.e.,the plate capacitance, the fringe capacitance, and the terminal capacitance. Comparedwith Raphael simulation as well as measurement data, the new capacitance model ac-curately predicts the capacitance value at28nm node, the max error is less than2%.The fringe capacitance and terminal capacitance become important in28nm node,which is about30%of total capacitance.The introduction of CuAl alloy seed is good for reliability. We discuss the effectof thermal treatment on interconnect wire from the diffuse of Al and the metal wirestructure. Al segregation at Cu/barrier interface can be observed from SIMS data,which can effectively depress electromigration. The grain size of Cu wire will increasewith the thermal temperature and thermal time. The grains in wide lines are larger than those in narrow lines. The wire resistance is close related to the grain size. |
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