| As the terminal of smart grid, smart meter is concerned about after smart grid being into the national "12th Five-year Plan". Smart meter control chip is the key component of smart meter as it has the most important function such as calculating the electricity tariffs, control, display, communication and so on. With the rapid development of IC in recent years, power has become the same important factor to restrain IC as area and timing constraint, the industry already has a low-power design methodology. This thesis discusses a low-power chip design implementation based on physical designing of digital part of Fudan Microelectronics smart meter control chip, and be successful in completing of the whole process from RTL to GDSII, the chip has completed the tapeout, testing and market testing, the test shows that the chip can work correctly, reach the requirement of the national smart grid, which also verifies the feasibility of low-power design methods used.The first part describes the composition of the CMOS circuit power consumption and the factors that affect them, and the dynamic power and static power consumption, as well as their contradictions. Describes the issue of power consumption used by the industry in different stages of design low-power means and focuses on the physical design phase of the low-power technology, select the best low-power optimization for plan with the consideration of the energy requirement of project, development costs, R&D cycle.The second part uses Synopsys back-end place and route tool IC Compiler to complete physical design of the project under the0.18um, describes the flow stage design in detail. In the design process using the low-power placement, low-power clock tree synthesis, low-power routing technology.The third part analyses the IR drop and power, the result shows that the chip has already achieved the basic goal of a low-power design.Finally, gives a summary and outlook, discusses the contributions and shortcomings of the thesis. |
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