Digital Back-end Design Of RF Chip With Optimizing IR-Drop And Clock Tree

With the rapid development of integrated circuit technology and manufacturing process,the feature size of transistor continues to scale down and the integration and the clock frequency are being improved much.More effect due to interconnect delay leads to the timing closure difficulties and increased power consumption.Furthermore the reliability issue on power mesh is introduced by more power consumption and parasitic resistances.Nowadays the requirements on backend design are much stricter than before.Therefore,a reasonable floorplan and a low power clock tree synthesis for timing closure are necessary to guarantee the functionalities and reliabilities of integrated circuits.In this thesis,the physical design and implementation of a RF communication chip were presented;especially the analysis and design of floorplan and clock tree synthesis were focused.The design of the RF chip floorplan was discussed with following the basic rules.Based on the feasibility analysis of power mesh,aiming at the potential problems of IR-drop and electromigration hot,several methods were proposed,which including increasing the number of VDD power supply I/O cells,equally distributing ground supply,and optimizing metal layers and width of power mesh.By doing so,the IR-drop was decreased and electromigration hots were eliminated.The clock tree synthesis of RF chip was accomplished by setting reasonable cell size and clock network parameters.The method of using “exclude pin” setting was utilized to resolve the setup time violation of divider.Combining the preliminary timing results and the characteristics of the chip,a low power clock tree synthesis strategy with inverter structure was proposed.The back-end design of the RF chip was completed in SMIC 0.18?m CMOS.With using the proposed IR-drop and clock tree optimization strategy and comparing with the traditional design,the power voltage drop was decreased from 30.72 mV to 13.68 mV and ground bounce decreases from 34.70 mV to 3.79 mV.The overall voltage drop including power and ground bounce accounted only for 1.06% of the supply voltage of 1.8V,far less than the design requirement of 3%.Meanwhile the total power consumption of the chip was reduced from 53.96 mW to 46.46 mW,which was 13.90% decreasing.Finally the chip was taped out and works well.And it has gone into full mask.