FPGA Realization Of Digital Front For Wireless Communication Stations

In the new generation of base station architecture, FPGA+DSP have been widely used with its scalable, modular and flexible. FPGA, with the ability of high-speed parallel processing and data transfer advantages, Combined with high performance DSP to achieve a base station system design which is low power and DC power supply in specific application scenarios.Digital filters, which plays an important role in digital signal processing system, is essential to eliminate noise and interference module. This system design in accordance with the requirements of the filter performance using FDAtool which is from MATLAB for filter design, to determine a combination of down-sampling filter implementations which is achieved in FPGA, this kind of design has taken into account the performance and resource consumption, to achieve the design and optimization goals.According to the analysis of the causes from deviation, the frequency offset compensation algorithm based on CORDIC IP core in the FPGA. At the same time a high-speed interfaces for SRIO study analyzed the problems of traditional bus and SRIO advantages in embedded systems, based on practical application of engineering to meet the requirements under the premise transmission rate in the FPGA1x SRIO, saving resources and power. And conducted between FPGA and DSP board-level debugging SRIO Internet to verify the desired design goals.