Optimal Design And Implementation Of Matched Filter Based On FPGA

Matched filer is the best linear filter with maximum SNR output. It equivalent tocorrelator is widely used in optimal reception of digital communication systems anddirectly influences the performance of the whole systems.This thesis discusses the principles and compositions of the digital matched filter,and has an insight into the structure. Subsequently, the detection and acquisitionprinciples of matched filter are introduced. Then the key parameters are determined, andthe simulation of matched filter is performed.The key elements of the digital matched filter are focused and optimized in order tofacilitate the implementation of FPGA with minimum resources on the premise thatoptimizations will not change the performance of the digital matched filter. Severalmethods for optimizing the matched filter are proposed, through the layers of comparison, thefinal scheme of parallel folded filter based on SRL16is adopted and using the TimeDivision Multiplexing technique and the special structure of the Virtex series devices ofthe Xilinx.Finally, the hardware design of matched filter is introduced.The system is achievedby useing FPGA.Illustrated by the final test the optimization system design andimplementation success.