Data Cache Research Based On Base Address Register Mapping

As a bridge between the memory and processor, Cache’s performance and power consumption have been a growing concern. In this thesis we force on the low power technologies for Cache, and have a research on memory access characteristics and zero-level data Cache, as a theoretical basic for the design in this thesis. The main content and innovations of the thesis include:1. Propose a method of data buffer access which based on base address register for embedded processors. Building locality accessing history between base address register and destination data dynamically during the execution of load instruction, and designing a base address register tracking buffer, which let load instruction get data immediately at decode stage. This method accelerates the speed of load instruction to get destination data, and avoids address calculating and cache accessing. The results of benchmark indicate that performance of processor with this method increases about3.7%averagely, and data cache power reduces about16.6%averagely.2. Propose architecture of zero-level data Cache which can reduce the power of Cache access and increase the performance of processor. This architecture bases on base address register mapping technology, and makes use of index tracking technology. Via adding a index tracker in decode stage and an address check table in load/store unit, the access latency of load instruction and Cache access power will be reduced. The results of benchmark indicate that data Cache power with this zero-level data Cache reduces about28%averagely and performance of processor increases about3.5%averagely. Compared with normal zero-level data Cache, performance of processor with this architecture increases about7.4%averagely, and the power of access Cache is the same.