Design And Verification Of The DSP Processor Data Cache

Cache can speed up the access to memory from DSP processor and enhance DSPperformance at the same time. However, it is regarded that cache is the main source ofpower consumption of the whole processor just because of its large area and high accessfrequency. Thus, to enhance the performance of the whole DSP processor, it is of greatsignificance to design a kind of cache that is of high performance and low power.Nowadays, it has become a hot issue to design such kind of cache.This thesis expounds a data cache with high performance and low powerconsumption. This kind of cache contains a line buffer to reduce the access frequencyfrom the CPU to cache, so as to decrease the power consumption. According to thebasic parameter, this thesis describes the system architecture of data cache, and designsthe cache in top-down style with VHDL language. The software VCS of SynopsisCompany is used to make function simulation of this cache. Finally, there is aconclusion that when a cache miss happens, data cache makes it possible to send datafrom external memory to the DSP core within6cycles, and refill the cache line within20cycles as well. In this way, the desgin can enhance the performance of DSP processorsignificantly.By running three benchmarks including FFT AC3and FIR, we’ve made aconclusion that the line buffer reduces the access frequency from DSP core to cache by35%, obviously decreases power consumption of the data cache. Now the data cachehas come into use, with the whole power consumption below0.5mW/MIPs.