The Design And Implementation Of Serial Rapidio Interconnect System

With the growing demand of system bandwidth in wireless communications, video processing and military field, a new type of high-speed serial interconnect technology began to gradually replace the traditional parallel bus. As one of the new type of high-speed serial interconnect technology, serial RapidIO is specially designed for embedded systems. Compared to traditional interconnect technologies, it is more flexible, stable and efficient.In this paper, the mainstream RapidIO interconnect system architectures are introduced. The Serial RapidIO specification is described by three parts--logic layer, transport layer and physical layer. Two RapidIO system interconnect solutions are proposed.For the point-to-point optical fiber communication of some cost-sensitive system, a low-cost solution based on the RapidIO protocol is proposed. This method achieves the upper logic protocol, physical layer protocol and fiber-optic transmission with hardware programming, high-speed transceiver and the optical module based on the FPGA Cyclone IV. According to the test results, this design uses less resource and has a reliable performance, the data throughput reaches1.25Gbps, and the design has been successfully applied in a communication system.The RapidIO interconnect systems based on the VPX architecture is designed for high-speed and high-performance software radio system. In addition to the RapidIO interface, hardware design also includes high-speed sampling circuits, DDR3memory interface and clock and power supply. FPGA RapidIO endpoint is implemented by Xilinx LogiCORE. DSP endpoint is implemented by the operating to the LSU registers.