Font Size: a A A

Research On The Scheme And FPGA Implmentation Of The Key Modules For A SDH Multifunction Tester

Posted on:2011-08-02Degree:MasterType:Thesis
Country:ChinaCandidate:L LiFull Text:PDF
GTID:2248330395957321Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
With the quick development of optical SDH networks and network equipments based on SDH, the relevant test instruments have found to be a huge application. A variety of SDH test equipments have developed at home and abroad. But the domestic equipment with limited functionality can not meet the increasing demands for testing, and the ones from abroad could not have been largely used in our development and testing of communications products because of untolerable high prise. Therefore, the further research of the core part for the tester, including the test data processor, the FPGA implementation of its key module-AAL5processing module and data transmission interfaces, has important practial value for breaking down foreign technology and price monopolization, and developing high-performance domestic SDH tester and the AAL5chip with our own Intellectual Property.This dissertation sponsored by the key projects of the State High Technology Research and Development Program(863Project), which named key techniques and experimental system of PCE-based multi-layer and multi-domain optical network.My work in this dissertation is the entension to application aspect of the project. On the analysis of the existing research on the SDH test at home and abroad, the overall realization scheme of a multi-function tester is proposed in this dissertation, which can be used to analyse the performance of the ATM and PoS (Packet over SDH) networks. The study emphasis is on the FPGA implementations of AAL5protocol, UTOPIA Level2, and UTOPIA Level3interfaces according to the specifications. By using the ALTERA Stratix-II FPGA, this dissertation implements the functions of send direction of AAL5protocol and the two interfaces with VHDL codes and completes their simulations. Simulations and analysis show that the implementations of all modules fully meet the requirements of the tester to be designed. Finally, the summary of whole dissertation is given and the issues to be studied further are also proposed.
Keywords/Search Tags:Synchronrous Digital Hierarchy Test (SDH Test), ATM Adaptation Layer Type5(AAL5), Universal Test&Operations PHY Interface for ATM (UTOPIA), Field Programmable Gate Array (FPGA)
PDF Full Text Request
Related items