Double-precision Floating-point Matrix Computing Unit Design Based On Fpga

Informational missile weapon system will adopt more and more advanced navigation and control technologies in the future, for example multimode complex homing guidance, more complex and accurate compensation algorithms of navigation, FIR filter widely used in multi-source signals acquisition and so on. Now, we mainly depend on general DSP to build the computer of missile. It’s hard to fulfill the request of high performance calculations. It will greatly improve the real-time characteristic, precision and reliability of missile control system by optimizing and implementing some complex missile navigation algorithms based on hardware.First of all, this dissertation refers to some correlative documents, analyzes the algorithms of strapdown inertial navigation, fixes on the scheme to develop and design the IP core of double floating-point matrix calculation, and partitions the IP core into some parts. Second, according to the IEEE754standard, this dissertation designs floating point adder, subtracter, multiplier, division and square root module by Verilog HDL in Spartan-6series FPGA. Third, the distributed calculation structure was designed by analyzing and studying the navigation algorithms. This dissertation newly designs a hardware-based architecture for IPs. The architecture based on pipeline structure, has multiple floating point calculators computing at the same time. Speed and area are balanced in the limited hardware resources. The structure includes a central control module and ten parallel floating-point basic arithmetic modules. The central control module is responsible for the order of algorithm. The peripheral modules can accomplish three operations of addition, subtraction, multiplication or Division, and one root operation at the same time. Based on AHB bus standard, matrix arithmetic IP interface is designed for exchange data with processor. These IP cores of quaternion matrix calculation, navigation calculation and inverse matrix calculation were implemented based on this structure.In the end, the IP cores were experimented on a FPGA chip of Xilinx. We compare the precision and velocity of these IP cores with the C6713B DSP’s. The calculation velocities of IP cores are more than ten times of DSP’s with the same precision.