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Design Of DC-DC Converter Embedded In SoC Of Nano-meter Process

Posted on:2014-06-04Degree:MasterType:Thesis
Country:ChinaCandidate:F HuFull Text:PDF
GTID:2252330401465449Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With rapid development in the recent decades, minimum line width of CMOStechnologies enters nanoscale, which makes integrated chips more highly integrated,more complicated and demand lower power consumption. More advanced technologyallows the circuits to be smaller and more energy saving while Consumers’ stricterrequirement of portable electronic products promotes miniaturization and highefficiency of the power supply. It becomes urgent that power management circuits aredesigned under newly CMOS technologies. These systems are mostly single-batterypower supply system, in order to meet the various power supply needs of all themodules, the PMU which stands for power management unit is proposed. As moreattention are drawn to the market of portable device, research on power managementunit is becoming more and more urgent, especially on those applicable in SoC. As thesame time, the DC-DC converter is the most basic and important prat.This thesis firstly introduces how nanoscale CMOS technology affects analog ICdesign, namely WPE and STI and analyses their impact on a specific technology and themethod to waken such impact. Then a whole design of a DC-DC converter IC ispresented, including the choosing of the inductor, the capacitor, the switch frequencyand the compensation, followed by the mathematical derivation and MATLABsimulation of mixed-signal Pseudo-Type III compensation. The last part elaborates thedesign of some key sub-modules and the simulation of sub-module and the entire circuit.The thesis emphasizes the influence of the nanoscale CMOS technologies and therealization of the mixed-signal Pseudo-Type III compensation.The layout of the IC designed is680μm*603μm and tapes out in standardnanoscale CMOS technology. The chips are tested after package and the results showsthat the output voltage is continuously adjustable from0.57to1.30V in the switchfrequency of2.25MHz. The line regulation and the load regulation in the range ofnormal input voltage are smaller the1%. The maximum efficiency achieves86%at theload of110mA.
Keywords/Search Tags:DC-DC Converter, Voltage Control, Pseudo-Type III Compensation, Nanoscale CMOS Technologies, High efficiency
PDF Full Text Request
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