The Design Of Synchronous Boost Converter And Its Macromodel Of Verilog-A

With the rapid development of portable electronic devices, power management IChas become one of the most important applications in integrated power semiconductorcircuit design. Power conversion efficiency is an important standard of measuringpower products. Among all the control modes, the DC-DC pulse width modulation(PWM) has been proved to be highly efficient, thus widely used in portable switchingpower supply chips.IC scale is increasing, which makes the R&D engineers encountered greatdifficulties with the application of EDA software when conducting system simulation.Such simulation takes much time and creates big data, which seriously affect theproduct design cycle. The integrated circuit macro model can be a great help todesigners. It can greatly reduce the amount of data, shorten the simulation time andeventually improve the product design cycle.According to market demand, a high efficiency synchronous step-up DC/DCswitching power management chip was designed. Macro model based on verilog-A wasestablished for part of the chip to solve the problems mentioned above, and was appliedto the overall circuit simulation.Before specific circuit design, this article first introduces the DC/DC convertertopology and basic working principle, and then introduce PWM (Pulse-WidthModulation), PFM (Pulse-Frequency Modulation) and PSM (Pulse-Skip Modulation),and finally analysis the existing problems and principle of synchronous rectification.As for circuit design, this article focuses on the five parts, including the referencecircuit, oscillator circuit, current detection circuit, delay circuit and protection circuit. Inthe design of the oscillator circuit, the value of the resistance and capacitance changewith the process, so trimming circuit is necessary.Verilog-A language, which is a mixed hardware description language, was used todesign macro model. In this section, we first briefly introduced Verilog-A, including thebasic grammatical structures, some keywords descriptions, some simple examples toincrease the understanding of the language. Part of the circuit was programmed after that.Hspice simulation tools in Candence EDA software were used to simulate thecircuits, both partly an systematically. Functional verification of Verilog-A program wasconducted then..This chip was taped out using NUVOTON5V CMOS process. Test results showthat the chip meets the all requirements, and the design goals were achieved.