Design Of A PFM Synchronous Rectification Boost DC-DC Converter With High Efficiency

With the continuous development of electronic equipment, the portable electronic equipment are becoming more and more convenient and enriching people’s life. All these electronic equipment are widely charged with batteries, so the battery-power has become the main trend, which sets higher requirements on power management chip. High precision, high efficiency, high integration, low cost, low power supply voltage, low power consumption and fast transient response are the important trend of the future power management chip. As the energy consumption increase, any electronic product is unable to avoid saving-energy, especially the DC-DC converter. Besides, the DC-DC converter work under the condition of light load most of the time, so it is great significant to study the high efficiency DC-DC converter under light load.This paper designs a high-efficiency synchronous boost PFM DC-DC converter with peak current-mode control, maximum on-time and minimum off-time logic control module. And the DC-DC converter can achieve adaptive restart. When the current exceeds the threshold, the chip can be protected by the internal soft-start circuit. When the system resumes, the chip can achieve the adaptive restart. which integrates the power tube NMOS and PMOS. Besides, the chip includes under-voltage lockout, over-temperature protection, over-current protection.The system is designed and simulated using Cadence and HSPICE, then taped out on South Korea east 0.35μm BCD process. We also test the chip using test instruments. The chip operates over an input voltage range from 2.0V to 3.3V and can boost a suitable 10V output voltage. The efficiency can reach as high as 85% at light load of 2mA. The also has excellent load regulation and line regulation. The quiescent current consumption is less than 30μA and the ripple of output voltage is less than 30mV. The chip can be used in 3D eyes driver and small LCD bias supply.