The Design Of ADS-B Signal Preamble Detection System Based On FPGA

Automatic dependent surveillance-broadcast (ADS-B) is a kind of airborne electronicequipment. ADS-B system can broadcast call sign, location, height, speed and otherparameters by airborne equipment. Because of the good data transmission function, ADS-Bcan be applied to various airspace surveillance and airport surface surveillance. Comparedwith radar surveillance, ADS-B has higher monitoring precision,faster nformation update rateand lower cost of maintenance.In the future, ADS-B technology will become the main way toreplace the radar aerial surveillance system. Therefore, receiving and processing of ADS-Bsignals is an important direction of the air traffic control system, has a very importantsignificance.These advantages of ADS-B makes this technology have great research value. Thesubject works on how to the receiver decode board. This paper first describes thedevelopment process of ADS-B system, makes the decoding measured ADS-B digitalbaseband signal as the main working target clear.Then this paper expounds the basic principleof ADS-B signal’s transmitting and receiving,and compares the different transmissionmodes of ADS-B system. Next,this paper explains the ADS-B header’s structure andencoded mode. Then, this paper introduces the theory and algorithm of ADS-B signal todetect the preamble. In order to be more easily achieving algorithm in hardware, this paperimproved it Finally, this paper introduces the ADS-B signal processing software platform andhardware architecture, clarifies how to achieve S model algorithm of ADS-B signal in theFPGA header extraction.The main work of this paper is to decode S model of ADS-B signal by studying thealgorithm of detecting the preamble.In the software, traditional algorithms need the datas tobe compared with each other repeated, it is not suitable for hardware implementation. Thispaper improved the header processing algorithm theory, the ADS-B signal header processingresults are verified by EDA simulation software.In the Hardware, This paper designed thehardware part of the header processing code board, Reasonable layout the hardware circuitwith FPGA as the main chip.Finally draw the circuit diagram and PCB, plate, welding,debugging, and ultimately header extraction function in hardware.In this paper, the basic realization way of header extraction is using Verilog programming language in Quartus II software platform to achieve header extraction algorithmand the program is downloaded to FPGA chip. The input signal will automatically retrieve8sheader ADS-B signal by processing chip program, And the112datas which is behind theheader signal will be stored in the RAM. The data signal which is stored in RAM will be usedby DSP chip, to obtain0,1yards which means representative aircraft information.Chip FPGAread these0,1code,and transfer to the pc through the serial port. PC deciphers the received0,1yards based on ADS-B encoding standard,displays readable aircraft information.