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The Design And Implementation Of High Speed Data Transmission Circuit Based On USB3.0

Posted on:2015-01-01Degree:MasterType:Thesis
Country:ChinaCandidate:Z M LiFull Text:PDF
GTID:2252330428458857Subject:Precision instruments and machinery
Abstract/Summary:PDF Full Text Request
The data recorder with mass capacity is very important airborne equipment, which ismainly used for massive data acquisition and storage during flight. For the amount of datareaches tens of GB, even hundreds of GB, it is very essential to improve transmission rate forlarge numbers of data. With5Gbps transmission speed, USB3.0interface has been widelyused in market, and becomes a bus standard for data exchanging between PC and externalequipment, and it has the characteristics of plug-and-play, high-speed transfer, backwardcompatibility. In this context, a kind of high speed data transmission system is designed inthis dissertation. We use Altera·s CYCLONE III·s FPGA as the control center, Micron DDR2SDRAM as a high speed and mass buffer for data transmission, and USB3.0system as a datacommunication with the computer interface.Firstly, the researching background, domestic and abroad development situation, andthe related protocol of USB3.0technology are introduced; Secondly, according to the taskrequirements of big capacitance data recorder, we design a FLASH memory, and construct ahigh speed data transmission system based on the combination of USB3.0, FPGA and DDR2SDRAM. Then we focus on the design of hard circuit and software. Through to perform thesignal integrity simulation and analysis between FPGA and DDR2SDRAM interface signals,we obtain the corresponding PCB design rules. In the software design part, combined withthe data transferring process, a high speed buffer based on FIFO inside FPGA and DDR2SDRAM is designed. Develop the USB3.0firmware, design GPIF II state machine in SlaveFIFO mode, completes the main control program with VHDL language. Thirdly, the testresults of ECC algorithm and high speed data transmission circuit are provided.This high speed data transmission circuit is designed in this dissertation for transferdata between the computer and data recorder via the USB3.0interface. The circuit can realize150MB data transmission. It solves speed tight bottles that restrict big capacitance data recorder performance improvement. In addition, this research in this dissertation also couldbe as a reference to the image data with high speed and high capacity.
Keywords/Search Tags:USB3.0, DDR2SDRAM, FPGA, signal integrity, high-speed data transmission
PDF Full Text Request
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