The Design Of The Arbitrary Waveform Generator Module Based On DDR2SDRAM

As a common source, the arbitrary waveform generator can generate conventionaland arbitrary waveforms meeting the needs of tests, and it has a wide range ofapplications in modern test systems. Now the core technology of waveform synthesis isthe direct digital synthesis technology, with sampling frequency and memory depth asits major performance indexes.High sampling frequency can guarantee high outputbandwidth, and large memory can reproduce the waveform details and complexwaveforms. With the increasing of the operating frequency and complexity of themeasured object, higher requirements are also put forward for the output waveformcomplexity and bandwidth of arbitrary waveform generator. Due to its low access speedand small storage capacity, conventional SRAM has significant limitations to be thewaveform memory, while as a new type of memories and boasting its fast access speedand large storage capacity, DDR2SDRAM is suitable for the research and applicationof high-speed and large memory technologh.Aiming at the questions above, this thesis mainly makes a study the arbitrarywaveform generator module design based on the DDR2SDRAM. The design workinclude: the waveform synthesis hardware circuit, FPGA logic. The main contents are asfollows:1. Waveform synthesis circuit design of high-Speed and large storage. According tothe read-write features of DDR2SDRAM, we analyze its application feasibility in twodifferent waveform synthesis structures (DDFS and DDWS) and eventually choose theDDWS method to synthesize the random waveform. According to the indexrequirements of the module, and starting from the function integration, using fieldprogrammable logic device (FPGA) to complete the module’s main function design, the"FPGA+DDR2SDRAM+high-speed DAC" architecture is adopted for the realizationof the waveform synthesis circuit, and the building of the hardware platform iscompleted.2. FPGA logic design. Mainly to complete the design of DDR2SDRAM controller,synchronize the cross-clock domain data in the system, and complete design of the address generator, decoder, DAC control module, etc. Through the FPGA logic control,the proper reading and writing of waveform data and the waveform output can berealized.3. Testing and verification. After designing appropriate test methods in accordancewith the module indicators and selecting relevant test equipment to build the testplatform, we have verified the performance indicators, and make an analysis of the testresults, so as to prove the rationality of our design.The test results show that, as for the arbitrary waveform generator module basedon the DDR2SDRAM, the final maximum sampling frequency is1GS/s, and thememory depth is128M.