The Research And Design Of RF Front-end Circuits For UHF RFID Reader Receiver

Automatic identification procedures have become indispensable in today’smanufacturing, distribution, purchasing and service industries. The barcode labelsrevolutionized the identification systems many years ago, but now become inadequatebecause of their low storage capacity and inability to be reprogrammed and therequirement of line-of-sight tag reading. Near-field inductive coupled RFID systemsare fully developed, but with limited data rate and read range. Designed for an extendrange (up to10m) and a faster read rate (up to640kbps), a technology using passiveRFID tags operating in the860-960MHz UHF band is gaining worldwide momentum,especially in the supply chain management applications[1][2]. This paper describes thearchitecture and implementation of a single-chip RFID reader receiver and the designof some main circuit modules, including the mixer, the crystal oscillator and thefrequency synthesizer. A lot of work is completed as follows:A900MHz zero-IF quadrature down-conversion mixer is designed with a sharedtransconductor stage and current injection technique, which is typed out in UMC0.18μm CMOS process. The chip area is1mm×1.1mm. The test results of the mixerare as follows: The mixer in1.8V voltage consumes a current of3.7mA, with thebandwidth from880MHz to940MHz, and measures a conversion gain of16.42dB, anIIP3of4.625dBm, a Noise Figure of15.2dB at100kHz. The chip can satisfy theperformance requirements of the reader.By using a quartz crystal as reference the high precision (less than100ppm) canbe obtained. So the crystal oscillator is designed as the frequency reference for thefrequency synthesizer. The structure of Pierce oscillator is choosed and analyzed inthis paper. A clear insight into the linear behavior, including the effect of losses, isobtained by means of the circular locus of the circuit impedance. A basic conditionfor oscillation and simple analytic expressions are derived in the lossless case forfrequency pulling, critical transconductance and so on. The effects of nonlinearitieson amplitude and frequency stability are analyzed. The crystal oscillator usesautomatic amplitude control loop to minimize power consumption and to eliminatethe effects of nonlinearities on frequency. The lock time is about1.2ms. The crystal oscillator phase noise is148dBc/Hz at100kHz offset and149dBc/Hz at1MHzoffset.A fractional-N frequency synthesizer is implemented for the RFID reader. Inorder to operate in a wide-band frequency range a switched-capacitors arrayvoltage-controlled oscillator and adaptive frequency calibration technique are used.The measured VCO tuning range is from880MHz to1.02GHz and the VCO gain is30MHz/V. A4-bit third-order single-loop ΣΔ modulator is used to reduce phase noiseand to meet a frequency resolution of less than200Hz. The lock time is less than100μs. The layout area is1.5mm×1.6mm. The PLL phase noise is93dBc/Hz at100kHz offset and123dBc/Hz at1MHz offset.