| The analog-digital converter(ADC) and digital-analog converter(DAC) has anirreplaceable position in signal conversion process. The speed of converter isrequired to be higher and higher because of the proposed ultra-wideband technology(UWB) and the faster and faster speed of data transmission, which is now needed tobe more than1GHz. However, the accuracy and speed of the converter have only asmall room for improvement in the designer’s efforts, a new structure of theconverter is proposed, which is called the time interleaved ADC(TIADC).The design of this dissertation is a2GSps6Bits TIADC, its clock signalsampling frequency is2GHz, with a1.8V power supply. Design consists of a6bit1Gsps Flash ADC, a bandgap reference, a MUX, and a sampling time deviationcorrection and the correction circuit of offset of comparator. After the aanalysis ofthe mismatch of TIADC, a correct circuit of the mismatch of the sampling clock isproposed. The correct circuit is to extract the sampling time error based on theprobability of zero across, the error is handled with the Digital correctionalgorithms, after the adjustment of the sampling clock by controlling the delay unit,the performance of the converter is improved. A foregrounding correction programthat the digital logic control current trimming technique is used to reduce thecomparator offset. After corresponding simulation the static performance of INL is0.65LSB, and the DNL is0.44LSB.when exit100ps timing mismatch, the SNR is32.1dB while the speed of the input signal is100MHz. the sampling clock mismatchdo not affect the performance of the converter largely. When the speed of the inputsignal is turned to500MHz,the SNR is enhanced for1.12dB with the clock skewcorrection.circuits design,simulation and layout are completed. After DRC, LVS, andParasitic extraction. After post simulation the static performance of INL is0.9LSB,and the DNL is0.76LSB, the SDFR is39.1dB while the speed of the input signal is16.6MHz.The post simulation results are consistent with the previous simulation,basically meet the design requirements. |
