Research And Application Of FPGA Remote Upgrade

As FPGA (Field Programmable Gate Array) is applied more and more widely andFPGA based on SRAM process can be conveniently upgraded by modifying theconfiguration memory, designers have been seeking to implement FPGA systemupgrade especially remote system upgrade.At present, the remote upgrade schemesbased on single chip microcomputer,ARM, CPLD or FPGA controller have beenproposed. But these solutions require an external controller to control the FPGA chipconfiguration which not only increase the probability of configuration error andcomplexity of circuit design, but also improve the system design cost.In order to overcome the deficiencies of the above programs, this paper proposes aprogram using TCP/IP protocol for remote upgrade data transmission andimplementing system upgrade in a single FPGA chip. In order to achieve this program,the following work has been completed in this paper:(1)Overall system designThe hardware and software requirements of using TCP/IP protocol to transmittingthe remote upgrade data were analyzed and embedded SOPC+uC/OS-Ⅱ+LwIPprogram was finally selected as the overall system design. This paper completed theformation of the of SOPC on-chip system, the transplantation into the Nios Ⅱ CPU ofμC/OS-Ⅱ RISC real-time operating system and LwIP protocol stack; to verify thecorrect of the transplantation, the author has written the test code in eclipse softwareand displayed the result in Nios Ⅱ console via the JTAG debugging tool and the resultproved the correctness of the transplantation.(2)System hardware platform designAfter analyzing the resources demand for remote upgrade system and functionalsystem, the author finished hardware circuit module division, the appropriate chipselection and the schematic design, PCB schematic design in Altium Designer software.Then the Circuit board was welded, tested and the problem in the design was solved toachieve the normal working of the hardware platform.(3)Ethernet transceiver chip IP core designAfter using hardware description language to design the code of Ethernetcommunication transceiver chip MAC sublayer IP core and generating the IPcomponents in Qsys tool, the test was held in the eclipse software, through the communication between the PC and the design of IP core and the result was showed inthe Nios Ⅱ the console window, which indicate that the design was correct.(4)Integration and authentication of the system designAfter Integrating the design of each functional part in a system, designing theremote system upgrade process and writing the test program, remote system upgradetest has been held in the laboratory LED screen control system and the result provedthat the FPGA remote upgrade system was successful.