Integrated Circuit Low-power Design-for-testability Analysis And Implementation

With the improvement of VLSI integration and complexity，especiallywith the rapid development of SoC.It brings more and more challenges toIC testing. Due to technology development and widespread use of a varietyof high-performance portable devices, the power consumption of electronicequipment has become an important aspect that must be of concern in thedesign and testing.The power consumption of the chip during testing isseveral times higher than the power consumption during normal operation,it has been proved in the study.There are several reasons for thisphenomenon,Firstly, in order to reduce the test complexity, Design ForTestability is usually in the normal operating mode to idle, to work onlyin the test mode;Secondly,the degree of correlation between the testvectors are often small;Finally,in a low power design of the chip, whenin normal mode, generally only a small number of circuit modules is running,but in the test mode, in order to improve the testing efficiency, whichrequires the node of the circuit flip as much as possible.This has resultedin excessive power consumption, thereby increasing the cost of chip testing,affect the performance of the circuit,the chip may even be damaged duringtesting. Therefore, to reduce the test power has become an important goalof the test development.A large number of low-power design studies are starting from the chipnormal mode of operation will lapse in test mode. This is because the purposeof the chip design is to make the internal node flipped in the shortesttime, and passed the these flip Information, there is a fundamental conflictwith the low-power design philosophy. In the testing process, the internalnodes of integrated circuit produce a large number of a flip within a veryshort time, which causes a series of power consumption issues as follow:Firstly,the power consumption when the test is too large will cause thetest chip overheating,the chip may be damaged because the temperature reasons;Secondly,in testing process, the large number of circuit fliprequire a higher current, and the lack of current supply may result in thecorrect chip cannot pass the test.In order to solve the problem of test power, academic and engineeringconducted a lot of research in the IC testing microprocessor test andsystem-on-chip testing areas.This article focuses on the principles and methods of low-power scantest technology and low-power built-in self-test technology, and thencombined with a specific project conducted a comprehensive analysis andimplementation of these two technologies, and finally describe and analyzethe results of the implementation of the project.