Research On Technology Of Design For Testability And Application

With the rapid development of microelectronic technique, high integration level of IC and increasing complexity of PCB, the traditional test models and test methods can't satisfy the times'request for test on account of the gigantic test expense. The method that test engineers develop their programs with the designed system can not adapt practical testing require. Owing to the above factors, the dissertation puts emphasis on researching structure design-for-testability of digital logic and memory, so as to alleviate the burden of ATE and effectively improve system's testability.First, the dissertation introduces definition and methods of design-for-testability (DFT) , the methods include special DFT and structured DFT is made up of boundary scan test and build–in self-test(BIST),and then researches SCOAP estimate and arithmetic and puts forward some methods of enhancing testability. Second , the thesis analyzes the principle, circuit and description language of boundary scan test .We use the technique of boundary scan in design for testability of 8-D trigger, and give BSDL program and emulator sequence of TAP controller. Third, the thesis puts high importance to studying the economic and applied method of design for testability, that is build–in self-test for digital system. BIST includes logic BIST ( LBIST ) and memory BIST(MBIST) . By putting test pattern generators and response analyzers into the circuit, the circuit with BIST function can generate test stimulation and analyze test response without outside support, and then can make the test and diagnosis of digital system become more quick and effective. The thesis introduces the principle , test algorithm and circuit of BIST,We design the LBIST of 8-bit ripple carry adder and the MBIST of 16*8 ROM and RAM.Test vectors generator, circuit under test , signature analyzers and controller of build–in-self test are realized in one chip with FPGA. The method is effective and high-speed to solve design for testability of Random Logic circuit and Embedded Memory which is demonstrated by using MAX+PLUS II software simulation. In a word,the design method of a sort of uniform IC DFT technique with low test cost and high fault coverage will meet the need of further development on IC design.