The Realization And Verification Of Technique Of Automatic Code Generation Of Clock Control Unit

Nowdays the IC design process requires a large amount of work to do becausedigital integrated circuits became high complexity. However structured design makesthe automation of RTL code possible. This paper researches a tool which generatesVHDL code of the clock control unit automatically and verifies of the code.This paper researches the technology of clock gate and multi-voltage. Based onthese technologies, this paper designs the structure of clock control unit to achieve theneed of clock in the mobile phone baseband chip system. The unit supplies the controlof clock source, sends the output clock and save the power. The unit can be dividedinto seven modules, they are the modules of clock gate, clock source control module,3G clock handshake module,4G clock handshake module, registers, multi-clockdomain selection module, multi-voltage module, divider module. This paper design atool to generate the code of clock generate unit according to the clock control unit’sarchitecture and function characteristics. This tool based on the powerful dataprocessing ability of perl to generate the VHDL code. Implementation of the toolconsists of three parts: the establishment of complete data storage module; thegeneration of codes of function modules; the fulfill of tool interface.At present, more than two projects have used this tool to get the codes of clockcontrol unit automatically. This tool ensures that the design codes are consistency withthe design files.This paper use the direct verification methods for the verification of clock controlunit. The automation of testcases are finished by extracting information from the datastorage module. The result of verification shows that the code generated by the tool areright and the tool save the time of design and verification.