Power Optimization On RTL Of Memory Control Unit Based On Clock Gating Technology

The rapid development of integrated circuits and its double growth of design scales every three years,making So C(System on Chip system-on-chip)power consumption is paid more and more attention by the industry.And the power consumption is same with speed and area that has become one of the most important factors in the chip design.At different levels of chip design,the power consumption estimation,analysis and optimization of the chip has gradually become a trend,and many IC companies are focusing on this trend.If the power estimation and the optimization can be done on RTL,we can acquire obvious power optimization for the total working scenario,so researchers constantly seeking a variety of methods to estimate and optimize the power of integrate circuit at RTL(register transaction level)design level.The core content of this paper is several methods of power optimization on RTL.The related factors of reducing power will be studied based on the power therories of integrated circuit in this paper.At the same time the methodologies of power estimation and power optimization are researched and summaried based on activity factors.There are some problems are raised.One is that it is difficult and takes long time to analysis power on RTL,the other is low efficiency of clock gating of the chip.To optimize the power on the whole working scenario,some working states of chip which are typical working states are summarized in this paper.The running time of every typical working states are analyzed and quantized to help to estimate and optimize power for the real working scenarios.The above methodology lay the foundation of the below methodologies of power analysis.It is that this paper build the algorithm of analyzing idle module for chip on each typical working state.This methodology can extract the idle modules semiautomatic.And it will reduce the time and release the designers' sources if the flow of power analysis is ued.After the deep study of clock gating technologies,the other power optimization methodology is raised to resolve the problem of low clock gating efficiency for integrate circuity.It is the algorithm that inserting self_clock gating for design based on the constraint of registers' toggle activities.It can get the best power optimization ideally.Andthe registers' toggle activities are coming from each working states' register toggle activities that is calculated with the states' weight of running time.This can reflect the registers' real average toggle activities on the whole working scenarios.This clock gating methodology can improve the efficiency of clock gating and reduce the dynamical power for the real working scenario of chips.The results of this thesis and the methodologies of power optimization have significant values of power analysis and optimization both in theoretical investigation and practical application.