Research On Built-in Self-test Of Embedded Memory

With the development of IP reuse technology,memory accounted for the proportion of the System on Chip is growing.Memory built-in self-test is the most commonly used memory test technology,but the traditional built-in self-test circuit based on the state machine fixed test algorithm and fault coverage in the circuit design phase,with the continuous improvement of process technology and the appearance of more complex faults,the flexibility of the test and fault coverage is severely limited.Due to the above reasons,this paper designed a programmable memory built-in self-test system based on instruction code to realize the coverage test for all single-port and dual-port faults,and can configure all the March and its derivative algorithms in the chip test phase to improve the test flexibility and fault coverage.The details are as follows:According to the target of PMBIST,a set of 18-bits programmable memory built-in self-test instruction is designed in this paper,which can realize the programmability of test algorithm,test data and test address.The instruction set structure is optimized to reduce storage of the instruction required by the achievement of test algorithm.Based on the designed instruction set,the circuit module is divided and the programmable built-in self-test system is designed,which mainly includes instruction access module,decoding and test vector generation module,test and result response circuit.The PMBIST was verified by the March LR and March A2PF algorithm based on the instruction set code.In the case of fault injection in the memory model,the PMBIST achieved the test of function.The built-in self-diagnosis circuit was added to the PMBIST and the fault information(fault cell address,fault data,and the March element that detected the fault)is detected and serial output to the ATE.Fault analysis is performed based on the test algorithm to improve the level of process and memory design.A built-in self-repair circuit architecture is designed for the PMBIST,by remapping to redundant storage resources according to the fault location information collected by diagnosis to realize redundant replacement repair of faulty cells.The functions of designed diagnostic and repair circuit are verified under VCS software.The PMBIST system is synthesis under the standard process,and the area is 3.1K gates.Compared with other research results,the PMBIST not only achieved dual-port fault test and fault diagnosis,but also the area overhead reduced by 0.3K logic gates.Finally,a test Wrapper compatible with IEEE std 1500 standard is designed for the embedded memory IP core,including Wrapper bypass register,Wrapper instruction register and Wrapper boundary register.The test Wrapper can perform six instructions(including serial or parallel memory test,serial or parallel external logic circuit test,bypass mode,etc.),can achieve a well test and control on the embedded memory IP core.The WBR input and output cell is designed respectively.The test Wrapper is synthesis under the standard process for 8K?16bits SRAM,the area accounted only 1.617%of the total area of the memory.Compared to other research results,the area overhead of designed test Wrapper was reduced by 2907?m~2.The designed test Wrapper is verified by the VCS software.The results show that the test Wrapper can execute serial test and bypass mode and other instructions well.