A Design Of Real-time Wireless Sensor Network System Based On FPGA

Wireless Sensor Network (WSN) technology is the research hotspot of Internet ofthings technology, which contains many node to make up of an ad-hoc network, and tocommunicate with each other.WSN is one important way to fuse the material world andthe communication world,which is getting the attention of a growing number ofresearch institutes.Due to its low data transfer rate, scope of wide-area monitoring, low cost, lowpower consumption, etc, the characteristics of WSN in military reconnaissance,business monitoring, natural reconnaissance, medical care, etc, has the extremelywidespread application prospect.WSN will greatly change the way of production ofhuman’s life in the future.Field Programmable Gate Array (FPGA) is a kind of custom ASIC circuits, whichfits small batch of circuit design, in the digital system, network system, communicationsystem and signal processing system.This design is used to build a wireless sensor network application system which isbase on the FPGA.The protocol of this system is self-built and one kind of modifiedRAP protocol.This protocol is an ad-hoc networks protocol and one-by-one jumpingroute struction.The system have three parts: many sensor node，one gather node and displaysoftware on PC.The nodes self-organized a low speed wireless net to gather thetemperature of the nature and transport to the PC’s software to display and store.Themain contend of this system is the program in the FPGA which is only only digit logiccircuit not the CPU controller.In the way of only digit signal processing,this system canbe a new way to make up of WSN nodes.The logic circuit design is based on the hardware description language VerilogHDL.The verification and filting of the logic circuit is completed in the Alteracorporation’s software platform QUARTUS II9.0.The achievement of the logic circuitis on the FPGA of EP1C3.The radio circuit used the chip of CC1100,whichcommunicates with FPGA through the SPI interface.The software on the PC uses the serial UART interface to contect the FPGA.