Implementation And Optimization Of Solid State Storage System Via PCIe Interface

With the rapid development of information technology, memory performance hasbecome a research hotspot. Traditional disk mechanical devices because of its limitationsin terms of performance, energy consumption increasingly unable to meet some of thedemand for high-performance applications. Based on NAND Flash (flash) SSD with lowpower consumption, non-volatile, high random read and write performance is very goodproperties, is gradually replacing the disk into the mainstream media.Commonly used solid-state disk interface has USB, SATA, etc. These interfacesbecause of their physical characteristics, to a certain extent, limit the SSD read and writespeeds, became SSD performance bottleneck. Therefore, the current high-performancesolid state disk interface research turned PCIe storage interface, full-duplex, multi-requestprocessing capabilities and processing power to the storage disorder caused greatlyimproved performance, and scalable interface bandwidth greatly enhance the chain roadspeed. Therefore, in many high-performance PCIe storage needs of the occasion has beenwidely used.NVMe (Non-Volatile Memory express) is a common logic layer protocol thatspecifies the means of communication between host and SSDs in PCIe solid state memory.In this paper, The point is how to construct a PCIe solid state storage system based onNVMe protocol, so that the host-side software and device-side solid-state storagesubsystem to communicate. Including the preparation of a Linux system driver enables thesystem to recognize the PCIe SSD and use as an ordinary disk. In the implementation, thehost side and solid-state disk controller side to pass through the message queue read andwrite commands, and uses DMA (Direct Memory Access) transmission of data. Inaddition, this paper presents a solid state disk performance optimization algorithms, themain function is to analyze the host-side upper layer software for solid state disk I/Orequests, read and write requests to read and write to extract frequency features, and useNVMe agreement an optimized register interface and command set and other advancedfeatures, according to statistics SSDs host logical block read and write requests featureinformation on the cache replacement strategy accordingly improvements will read highfrequency logic blocks into the cache for while the low frequency of the read-write logicblock swap out the cache, thereby enhancing the cache hit rate. Experimental results showthat the algorithm improves the cache hit rate and reduce the number of data that is writtenback to NAND FLASH, and thereby increasing the SSD lifespan.