Near-Threshold Standard Cell Research

Nowadays, the miniaturization and intelligent of electronic products are resulting in anincreasingly high demand of the area, power dissipation and speed. It can be seen that because ofthe lighter, thinner and high-speed processing of modern electronic products, the designers tend tohave a high request for area and speed, but pay less attention to the problem of power dissipation.However，the development of the integrated circuit should be based on low power dissipation.First of all, in this thesis, it introduces the background theory knowledge of the CMOS lowpower dissipation and standard cell; also it analyzes the design of near-threshold circuits and howto apply this technology to standard cell. Reducing the supply voltage is an effective way todecrease the power dissipation, while the delay of the circuit will increase. The delay of the circuitbetween the power supply voltage and threshold voltage increases linearly. When the power supplyvoltage is less than the threshold voltage, the delay will increase in index situation. In this thesis, itadopts the SMIC130nm technology to develop near-threshold standard cell package, trades offbetween power dissipation and delay, and leads to energy delay product or power delay product. Inthis thesis, much attention to study the characteristics of near-threshold gates, full adder and triggercircuits according to the different supply voltage, and explores the optimal value of the supplyvoltage. According to the simulations of all the circuits with HSPICE, it can be seen that the energydelay product will reach a minimum when the voltage is from0.8V to0.9V(the standard supplyvoltage is1.2V).Three innovation points are presented as follows:(1) In this thesis, it raises a new optimal circuit which is adequate for the near-threshold logic.The author proposes a novel hybrid circuit according to the improvement and combination ofthe internal logic.(2) Compared with the circuit in commercial package, in this thesis, standard cell packagecircuit will decrease energy dissipation effectively, and even has a shorter delay.(3) In this thesis, near-threshold technique is applied to the standard cell package. As near-threshold technique has been brought up shortly, theory technology and parameter model arenot established, this thesis tends to explore and study near-threshold circuits, and apply themto the standard cell. Presently, this technology has not been reported.In this thesis, it presents the new structure XOR/XNOR gates in the near-threshold circuitdesign, and applied them to the combination of the circuit. Besides, the design of near-threshold standard cell verifies the simulation.8-bit multiplier is designed through synthesis, place and routetools. The experiment proves that power dissipation in low-power dissipation cells is much lowerthan commercial package units. According to the principle of building a database of near-thresholdstandard cell, the specific structure of this thesis can be simply divided into the following threeparts:In this thesis, it analyses the theoretical basis of the near-threshold circuit with low-powerdissipation. It surveys the typical XOR/XNOR gate, and CPL logic circuits supply voltage energydissipation, delay, and energy delay product (EDP) characteristics. There is a minimum EDPamong them, and the corresponding point of the supply voltage is the optimal voltage.In this thesis, it analyzes the circuit design that is suitable for near-threshold standard cellpackage. Standard cell circuits which are proposed in this thesis include basic gates, full adder andtriggers, searching for a suitable circuit structure to optimize low leakage power dissipation, andmaking a comparison with the commercial cell circuit.In this thesis, it analyzes the construction and application of the near-threshold standard cell.Firstly, layouts of complete standard cells are drawn. Then the layout placement and routingdatabase are designed. Finally, design standard cells through integrated library emulation libraryare extracted. Near-threshold standard cells in this thesis are designed based on ASIC design. Inthis thesis, the correctness of the effect of low-power dissipation as well as the physical rules fromlogic synthesis to layout and wiring are verified.