Design And Implementation On The Soft IP Cores Of Low Speed Serial Communication Bus

With the integrated circuit design to the system-level design stage, the SoC designwhich support by hardware-software combined design, IP core reuse and ultra-deepsubmicron technology has become VLSI’s development direction. Other hand, the serialcommunication bus has been applied in more and more chips because of its simple structure,saving transmission line and lower cost. In this paper, we design three reusable soft IP coresof the typical serial communication bus, which is accord with the development direction ofthe SoC design technology and has practical value.The1-Wire bus is a technology of Dallas Semiconductor Corporation, which uses onesingle line to transmit clock and data. The I~2C bus is launched by Philips Semiconductorswhich defines two bidirectional signal lines and supports multi-host system. The SPI bus isdesigned by Motorola which can complete the full-duplex synchronous communication byfour lines. We analysis and comparison of several common serial communication bus andintroduce the standard protocols of1-Wire bus, I~2C bus and SPI bus firstly. Then make thedesign goals and define the configuration parameters according to the chip requirements.Use the top-down design methodology to divide the module and define the interface timing.Then write the RTL code of the IP cores with Verilog HDL. Finally, simulate in the BFMbased verification environment and FPGA prototype, synthesize with Huahong-NEC0.35um library.With the same interface and a large number of configuration parameters, the IP coresin different protocol can meet different application requirements.