The Optimization Design And Verification Of High Performance Secondary Cache In Heterogeneous Multi-core DSP

DSP is a digital signal processing having a micro-processor chip, which is played akey role in today’s digital processing system. Current, DSP has been widely used inmany fields of national defense military, home appliances, engineering controls, mobilecommunications.In recent years, the development of DSP very quickly, in all aspects of theapplication has been very good about its performance requirements are also graduallyimproved, may encounter a "memory wall" so as to bring development bottleneckproblem, to solve it kind of problem, we use multi-level Cache structure. WhereinL2Cache Cache and played in the connection piece chip memory effect, L2Cachestructure using "Cache+RAM", so the design of a high performance and efficientL2Cache is necessary.X-QDSP is my own design of a high-performance multi-core DSP chip．Thefrequency of DSP controller call achieve500MHz.It adopts Very Long InstructionWord (VLIW) architecture and multiple level memory structure.X-QDSP uses two levelmemory structure on chip.The total of multiple level memory structure is4MB,and thesecondary memory is a1MB “Cache+RAM” memory. Each DSP core is256KB,Adopted the "Cache+RAM" structure so configurable, you can adjust the size of theRAM and Cache proportion L2Cache according to application needs. Articles forhigh-speed and efficient performance L2Cache were designed and implemented, andtested to verify the performance of its functions, specifically made the followingaspects:1. General design of the current Cache analyzed, discussed the multi-faceted inDSP Cache some performance and technology.X-QDSP is based on X-QDSPmonocytes DSP,with the structure characteristics of a multi-core DSP andrequirements.and proposed performance optimization plan.we complete the multi-coreDSP private L2function design and logical design.2. It improve the interface design which between private L2and the nextmemory.We simplify the miss data path coming into internal chip by rebuilding the L2and EMIF components of X-QDSP and redesigning the interface logic of L2andEMIF．Furthermore，such a nleasure can increase burst length of EMIF when ittransport data to L2to shorten the time of data staying in mid-transporting state,whichlargely reduce the latency of L2’s miss latency．3. For X-QDSP the EDMA move data between on-chip low efficiency of theshortcomings of the protocol interface between L2and EDMA optimized. EDMAability to read/write operations in a buffer was added after the water processing, parallel processing can be improved, the memory access latency is reduced. Thisimprovement greatly improving the efficiency of data movement EDMA.4． To assure the functional correctness of L2Cache， we adopt differentverification strategys. Using hierarchical verification carried out on L2module-levelfunctional verification，the L2Cache unit is verified in module level at first and isverified in system1evel in X-QDSP at last.develope a relatively complete testscheme，and complete L2Cache’s functional verificmion.The design of X-QDSP complete the private L2controller function expansion.Itincrease efficiency of the Cache level two access memory,and the comleting of a varietyof Cache operation.It improves the processing mode of DMA two memory access.Simulation results show that the optimized DSP improves the overall performance of10%or more, the X-QDSP L2satisfy design requirements.