Design And Research Of Cache Verification Platform Based On UVW

With the continuous development of large-scale integrated circuit technology,the scale of integrated circuits continues to increase,and the amount of RTL code is also greatly increased.While the division of designers is becoming more detailed,functional modules are refined into more sub-modules of specific functions,which caused the difficulty of verification has increased significantly and time-consuming has increased dramatically.Traditional verification methods can no longer meet the requirements of current digital integrated circuit verification for development time-consuming,development cost,and reliability.ASIC developers urgently need to adopt more efficient and reliable verification methods.This paper builds a verification platform for a RISC-V instruction set CPU's non-blocking Cache.The digital circuit with the Cache structure has a large state space,and it is difficult to cover all the functional points in the verification process,so the verification takes a lot of time and it is difficult to cover the boundary condition.The verification platform built by this project adopts the UVM verification methodology with more reusability and richer function library,and utilizes the phase,sequence and factory mechanism of UVM integration to realize a more flexible,easy way to maintain and expand verification environment.Firstly,this paper analyzes the memory access process of the instruction set of the CPU under test,the bus working mechanism,and the mechanism of data consistency,and specify the function points to be tested.Then,using UVM's sequence mechanism to design efficient verification case,write specific test case for each function point,and construct a suitable interface.The testcase generator,driver,monitor and scoreboard module are designed to connect the components through the TLM mechanism,meanwhile the function bus model BFM is written to encapsulate the cache access instruction and bus interface into tasks containing configuration information.Finally,the verification component is abstracted out of the parameterized port to create a hierarchical library and bus function model for future chip verification of similar structures.The verification platform can meet the requirements of functional verification coverage in a relatively fast time and meet the requirements of reusability.In addition,this paper proposes a Po W mechanism based on the digital chip verification process to replace the SHA256 operation commonly used in current blockchain applications.At present,the cryptocurrency distributed accounting node consumes a large amount of energy and computing resources to calculate meaningless SHA256 caculations each year,and the Po W mechanism proposed in this paper will reduce the electricity-consuming and solve the problem to some extent.In addition,the current cryptocurrency or blockchain applications are faced with the defect of reduced security caused by the decline of network-wide computing power.The Po W mechanism proposed in this paper makes the distributed accounting node not only able to obtain contention rights,but also able to trade the verification ouput with the publisher of the verification task to obtain additional revenue,which will reshape the ecological structure of the cryptocurrency industry and alleviate the shortcomings of reduced security caused by rapid decline in computing power.