Research And Implementation Of Human Head Detection Based On FPGA

The technology of detection about human head plays an important role in the field ofcomputer vision, especially, in the field of flow monitoring, security monitoring, accessingcontrol. This technology makes a great social and economic contribution. Human headdetection has a widely application prospects and research value, it attracts lots of focus in thedirection of computer vision.This paper mainly researches on human body’s infrared image and designs the algorithmof extracting target in the infrared image. Also, the paper based on the model design andcompletes the implementation of FPGA. The main content is following:Firstly, in order to conclude the basic characteristics of infrared image, the imagingprinciple of infrared image should be strictly researched. The mainly task of this paper is thatfocus on the noise of infrared image and analyses the image’s contrast. By comparing thehistogram of the infrared image with visible light image’s, this paper analyses andsummarizes the information of gray level distribution about the infrared image. ThroughMatlab, the algorithm of infrared image processing researched and designed according to thecharacteristics of infrared image.Secondly, after researched the basic characteristics of infrared image, the median filter isused to filter out the noise of infrared image, and the method of gray piecewise-lineartransformation is used to enhance the image’s contrast. And then, through the morphologyprocessing operation extract the head contour feature. In this paper, the value of the contour’seffective area, maximum length and maximum height should be calculated. The above threeparameters can be used to distinguish whether the target area is the human’s head andstatistics the number of human head.In the FPGA design and implementation processing, this paper based on Simulink modeldesign and constructs Matlab algorithm in visual platform. The platform can combine withSystem Generator which is Xilinx’s FPGA development tool. The FPGA implementation forimage processing completed in this system tool, and the system tool generates the VHDLhardware description language files that can be recognized by FPGA.Finally, this paper uses the software tools ISE to generate bit stream file and verifies theeffect of the algorithm on the experimental development board. The experimentaldevelopment board adopts Canada Lyrtech SFF SDR base band development board.